The present invention relates to a new slurry pad configuration, such as those used to polish semiconductor devices, to methods of manufacturing same, and to an apparatus used in such manufacture.
Semiconductor devices, such as, but not limited to, semiconductor-on-insulator (SOI) structures are prepared such that a relatively flat semiconductor layer is available, on which electronic components are formed. SOI technology is becoming increasingly important for use in displays, including organic light-emitting diode (OLED) displays, liquid crystal displays (LCDs), active matrix displays, integrated circuits, photovoltaic devices, thin film transistor applications, etc.
The semiconductor material most commonly used in semiconductor-on-insulator structures has been silicon. SOI structures may include a thin layer of substantially single crystal silicon (generally 0.05-0.3 microns in thickness but, in some cases, as thick as 5 microns) on an insulating material. The state of the art processes for forming TFTs on polysilicon result in silicon thicknesses on the order of about 50 nm.
As will be discussed later herein, the silicon layer thickness may adjusted through controlling the process parameters of bonding the silicon layer onto the substrate (e.g., a glass or glass-ceramic substrate). In display applications, the silicon layer thickness is typically in the 50-150 nm range. In addition to silicon layer thickness, the surface roughness of the silicon layer is critical to obtaining high performance TFTs. Surface roughness is typically in the 1-10 nm range just after bonding the silicon layer to the substrate (a so-called “as fabricated” SOI). Thus, post processes are typically carried out to reduce the semiconductor (silicon) layer thickness and to reduce the layer roughness. These processes will be discussed below.
The SOI abbreviation is used herein to refer to semiconductor-on-insulator structures in general, including, but not limited to, silicon-on-insulator structures. Similarly, the SiOG abbreviation may be used to refer to semiconductor-on-glass structures in general, including, but not limited to, silicon-on-glass and/or silicon on glass-ceramic structures. SOI structures encompass SiOG structures.
Various ways of obtaining SOI structures include epitaxial growth of silicon (Si) on lattice matched substrates. An alternative process includes the bonding of a single crystal silicon wafer to another silicon wafer on which an oxide layer of SfO2 has been grown, followed by polishing or etching of the top wafer down to, for example, a 0.05 to 0.3 micron layer of single crystal silicon. Further methods include ion-implantation methods in which either hydrogen or oxygen ions are implanted either to form a buried oxide layer in the silicon wafer topped by Si in the case of oxygen ion implantation or to separate (exfoliate) a thin Si layer to bond to another Si wafer with an oxide layer as in the case of hydrogen ion implantation.
The former two methods have not resulted in satisfactory structures in terms of cost and/or bond strength and durability. The latter method involving hydrogen ion implantation has received some attention and has been considered advantageous over the former methods because the implantation energies required are less than 50% of that of oxygen ion implants and the dosage required is two orders of magnitude lower.
U.S. Pat. No. 5,374,564 discloses a process to obtain a single crystal silicon film on a substrate using a thermal process. A silicon wafer having a planar face is subject to the following steps: (i) implantation by bombardment of a face of the silicon wafer by means of ions creating a layer of gaseous micro-bubbles defining a lower region of the silicon wafer and an upper region constituting a thin silicon film; (ii) contacting the planar face of the silicon wafer with a rigid material layer (such as an insulating oxide material); and (iii) a third stage of heat treating the assembly of the silicon wafer and the insulating material at a temperature above that at which the ion bombardment was carried out. The third stage employs temperatures sufficient to bond the thin silicon film and the insulating material together, to create a pressure effect in the micro-bubbles, and to cause a separation between the thin silicon film and the remaining mass of the silicon wafer. (Due to the high temperature steps, this process does not work with lower cost glass or glass-ceramic substrates.)
U.S. Pat. No. 7,176,528 discloses a process that produces an SiOG structure. The steps include: (i) exposing a silicon wafer surface to hydrogen ion implantation to create a bonding surface; (ii) bringing the bonding surface of the wafer into contact with a glass substrate; (iii) applying pressure, temperature and voltage to the wafer and the glass substrate to facilitate bonding therebetween; and (iv) cooling the structure to a common temperature to facilitate separation of the glass substrate and a thin layer of silicon from the silicon wafer.
By adjusting the implant energy, the semiconductor (e.g., silicon) layer thickness may be reduced to 300-500 nm if there is no oxide on the silicon surface before implantation, which is desirable for the SiOG process. From 300-500 nm, the thickness of the layer should be reduced to less than about 100 nm.
The resulting SOI structure just after exfoliation might exhibit surface roughness (e.g., about 10 nm or greater), excessive silicon layer thickness (even though the layer is considered “thin”), and implantation damage of the silicon layer (e.g., due to the formation of an amorphized silicon layer). The amorphized silicon layer may be anywhere from 50-150 nm in thickness and should be removed to obtain desired electronic properties for the later formed electronic components.
Chemical mechanical polishing (CMP) is a typical process to reduce the thickness of the silicon layer, to reduce the roughness of the silicon layer, and to remove the amorphized silicon layer after the silicon layer has been exfoliated from the donor silicon wafer. CMP for the SiOG structure application is accomplished using abrasive slurries coupled with a textile polishing pad (which is sometimes fibrous) saturated with such abrasive slurry. The slurry is a mixture of abrasive particles and a liquid carrier, which may be de-ionized water. The polishing pad is bonded (via adhesive) to a rotating platen. The SOI structure to be polished and the polishing pad are subjected to a stream of pumped slurry, and the polishing action is accomplished by forcing the abrasive charged polishing pad against the semiconductor material of the SOI, resulting in material removal and subsequent polishing of the semiconductor surface.
In most cases, both the platen and SOI structure to be polished are in a flat configuration. The polishing pad is formed and assembled to the platen such that the resulting pad surface is smooth and uniform, with no wrinkles or surface irregularities, which would otherwise create problems with the polishing uniformity. In the case of a flat polishing pad, it is a relatively straight forward task to cut and mount the pad to a flat polishing platen. The form of the pad is cut to conform to the contour of the platen (which is flat), and the pad is bonded to the platen with a pressure sensitive adhesive. In most cases, the polishing pads and the platens (and bonnets thereof) are of flat, circular geometry.
In more recent developments, the polishing pad is mounted on a semi-spherical bonnet that allows tangent tool contact polishing of spherical shapes such as lenses. The tangent tool contact processes can also be used to polish flat surfaces, such as SOT structures. This is commonly performed by deterministic polishing, an abrading process in which the contact area of the polishing pad is substantially smaller that the area of the SOI structure needing polishing. The material removal process is performed by rotating the bonnet (and attached polishing pad) and simultaneously moving it in a predetermined scanning pattern along the contour of the semiconductor layer of the SOI. Although different scanning patterns are available, the most common pattern is a series of closely spaced parallel lines (a raster), similar to the line pattern scanned on a cathode ray tube of a traditional television set.
The requirements for SOI thinning and roughness reduction are quite stringent. It would be desirable for the final semiconductor layer thickness to be controlled with an accuracy of about ±8 nm. The radius of curvature of the semi-spherical bonnet introduces a challenge as to mounting a flat polishing pad firmly to the radiused bonnet in a smooth fashion with no wrinkles that would adversely effect the polishing process. Wrinkles and/or other polishing pad irregularities may adversely effect the polishing process just as deviations in the rotation of the bonnet have a profound effect on material removal. It will be appreciated that any eccentricity in the polishing pad rotation (from the bonnet itself, wrinkles in the pad, registration problems, etc.) will result in thickness variability in the semiconductor layer. It has been found that bonnet eccentricity alone can result in thickness variability of about 15 nm, which is larger than the desired layer thickness tolerance. Additional irregularities from wrinkles in the polishing pad may significantly increase the variability.
The conventional technique for forming semi-spherical polishing pads is to cut a circle from sheet material, soften the material with acetone (or a similar solvent), and then press the pad in a two-part mold. The mold includes a bottom mold section having a convex surface and a top mold section having a corresponding concave surface. FIG. 1 illustrates the prior art semi-spherical pad 10 after the top mold has been removed. Note the wrinkles 12 at the peripheral edge of the pad 10.
In view of the foregoing, there is a need in the art for new methods and apparatus for producing a semi-spherical polishing pad.